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Features
* * * * * * * * * * *
Full Compliance with USB Spec Rev 1.1 Four Downstream Ports Full-speed and Low-speed Data Transfers Bus-powered Controller Bus-powered or Self-powered Hub Operation Per Port Overcurrent Monitoring Individual Port Power Control USB Connection Status Indicators 5V Operation with On-chip 3.3V Format 32-lead SOIC and LQFP Green (Pb/Halide-free/RoHS Compliant) Package Options Available
Overview
Introduction
The AT43312A is a 5 port USB hub chip supporting one upstream and four downstream ports. The AT43312A connects to an upstream hub or Host/Root Hub via Port0 and the other ports connect to external downstream USB devices. The hub re-transmits the USB differential signal between Port0 and Ports[1:4] in both directions. A USB hub with the AT43312A can operate as a bus-powered or self-powered through chip's power mode configuration pin. In the self-powered mode, port power can be switched or unswitched. Overcurrent reporting and port power control can be individual or global. An on-chip power supply eliminates the need for an external 3.3V supply. The AT43312A supports the 12-Mb/sec full speed as well as 1.5-Mb/sec slow speed USB transactions. To reduce EMI, the AT43312A's oscillator frequency is 6 MHz even though some internal circuitry operates at 48 MHz. The AT43312A consists of a Serial Interface Engine, a Hub Repeater, and a Hub Controller.
Self- and Buspowered USB Hub Controller AT43312A
SOIC
PWR2 PWR3 PWR4 VCC5 VSS OSC1 OSC2 LFT TEST OVC4 OVC3 OVC2 OVC1 LPSTAT SELF/BUS STAT4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PWR1 DP4 DM4 DP3 DM3 VSS DP2 DM2 CEXT DP1 DM1 DP0 DM0 STAT1 STAT2 STAT3
LQFP Top View
DM3 VSS DP2 DM2 CEXT DP1 DM1 DP0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
DP3 DM4 DP4 PWR1 PWR2 PWR3 PWR4 VCC5
1 2 3 4 5 6 7 8
DMO STAT1 STAT2 STAT3 STAT4 SELF/BUS LPSTAT OVC1
VSS OSC1 OSC2 LFT TEST OVC4 OVC3 OVC2
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The Serial Interface Engine's Tasks are:
* * * *
Manage the USB communication protocol USB signaling detection/generation Clock/Data separation, data encoding/decoding, CRC generation/checking Data serialization/de-serialization Providing upstream connectivity between the selected device and the Host Managing connectivity setup and tear-down Handling bus fault detection and recovery Detecting connect/disconnect on each port Hub enumeration Providing configuration information to the Host Providing status of each port to the Host Controlling each port per Host command
The Hub Repeater is Responsible for:
* * * *
The Hub Controller is Responsible for:
* * * *
Figure 1. Block Diagram
UPSTREAM PORT PORT 0
HUB CONTROLLER
SERIAL INTERFACE ENGINE
HUB REPEATER
ENDPOINT 0 ENDPOINT 1
PORT 1
PORT 2
PORT 3
PORT 4
TO DOWNSTREAM DEVICES
Note:
This document assumes that the reader is familiar with the Universal Serial Bus and therefore only describes the unique features of the AT43312A chip. For detailed information about the USB and its operation, the reader should refer to the Universal Serial Bus Specification Version 1.1, September 23, 1998.
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Pin Assignment
Type:
I = Input O = Output OD = Output, open drain B = Bi-directional V = Power supply, ground
Table 1. 32-lead SOIC Assignment
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Signal PWR2 PWR3 PWR4 VCC5 VSS OSC1 OSC2 LFT TEST OVC4 OVC3 OVC2 OVC1 LPSTAT SELF/BUS STAT4 Type O O O V V I O I I I I I I I I O Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Signal STAT3 STAT2 STAT1 DM0 DP0 DM1 DP1 CEXT DM2 DP2 VSS DM3 DP3 DM4 DP4 PWR1 Type O O O B B B B O B B V B B B B O
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Table 2. 32-lead LQFP Assignment
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Signal DP3 DM4 DP4 PWR1 PWR2 PWR3 PWR4 VCC5 VSS OSC1 OSC2 LFT TEST OVC4 OVC3 OVC2 Type B B B O O O O V V I O I I I I I Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Signal OVC1 LPSTAT SELF/BUS STAT4 STAT3 STAT2 STAT1 DMO DP0 DM1 DP1 CEXT DM2 DP2 VSS DM3 Type I I I O O O O B B B B O B B V B
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Signal Description
OSC1 OSC2 LFT Oscillator Input. Input to the inverting 6 MHz oscillator amplifier. Oscillator Output. Output of the inverting oscillator amplifier. PLL Filter. For proper operation of the PLL, this pin should be connected through a 2.2 nF capacitor in parallel with a 100 resistor in series with a 10 nF capacitor to ground (VSS). Hub Power Mode. Input signal that sets the bus or self-powered mode operation. A high on this pin enables the self-powered mode, a low enables the bus-powered mode. Local Power Status. In the self-powered mode, this is an input pin that should be connected to the local power supply through a 47 k resistor. The voltage on this pin is used by the chip for reporting the condition of the local power supply. In the bus-powered mode, this pin is not used. Upstream Plus USB I/O. This pin should be connected to CEXT through an external 1.5 k pull-up resistor. DP0 and DM0 form the differential signal pin pairs connected to the Host Controller or an upstream Hub. Upstream Minus USB I/O. Port Plus USB I/O. This pin should be connected to VSS through an external 15 k resistor. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream USB devices. Port Minus USB I/O. This pin should be connected to VSS through an external 15 k resistor Overcurrent. This is the input signal used to indicate to the AT43312A that an overcurrent is detected at the port. If OVCx is asserted, AT43312A will assert the PWRx pin and report the status to the USB Host. Power Switch. This is an output signal used to enable or disable the external voltage regulator supplying power to a port. PWRx is de-asserted when a power supply problem is detected at OVCx. Connect Status. This is an output pin indicating that a port is properly connected. STATx is asserted when the port is enabled. External Capacitor. For proper operation of the on chip regulator, a 0.27 F capacitor must be connected to this pin. Test. This pin should be connected to a logic high for normal operation. 5V Power Supply. Ground.
SELF/BUS
LPSTAT
DP0
DM0 DP[1:4]
DM[1:4]
OVC[1:4]
PWR[1:4]
STAT[1:4]
CEXT
TEST VCC VSS
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Functional Description
Summary
The Atmel AT43312A is a USB hub controller for use in a standalone hub as well as an add-on hub for an existing non-USB peripheral such a PC display monitor or keyboard. In addition to supporting the standard USB hub functionality, the AT43312A has additional features to enhance the user friendliness of the hub. The AT43312A's upstream port, Port0, is a full-speed port. A 1.5 k pull-up resistor to the 3.3V regulator output, CEXT, is required for proper operation. The downstream ports support both full-speed as well as low-speed devices. 15 k pull-down resistors are required at their inputs. Full-speed signal requirements demand controlled rise/fall times and impedance matching of the USB ports. To meet these requirements, 22 resistors must be inserted in series between the USB data pins and the USB connectors.
USB Ports
Hub Repeater
The Hub Repeater is responsible for port connectivity setup and tear-down. It also supports exception handling such as bus fault detection and recovery, and connect/disconnect detection. Port0 is the root port and is connected to the root hub or an upstream hub. When a packet is received at Port0, the AT43312A propagates it to all the enabled downstream ports. Conversely, a packet from a downstream port is transmitted from Port0. The AT43312A supports downstream port data signaling at both 1.5 Mb/s and 12 Mb/s. Devices attached to the downstream ports are determined to be either full-speed or lowspeed depending which data line (DP or DM) is pulled high. If a port is enumerated as low-speed, its output buffers operate at a slew rate of 75 - 300 ns, and the AT43312A will not propagate any traffic to that port unless it is prefaced with a preamble PID. Lowspeed data following the preamble PID is propagated to both low- and full-speed devices. The AT43312A will enable low-speed drivers within four full-speed bit times of the last bit of a preamble PID, and will disable them at the end of an EOP. Packets out of Port0 are always transmitted using the full-speed drivers. All the AT43312A ports independently drive and monitor their DP and DM pins so that they are able to detect and generate the "J", "K", and SE0 bus signaling states. Each hub port has single-ended and differential receivers on its DP and DM lines. The port I/O buffers comply with the voltage levels and drive requirements as specified in the USB Specifications Rev 1.0. The Hub Repeater implements a frame timer which is timed by the 12 MHz USB clock and gets reset every time an SOF token is received from the Host.
Serial Interface Engine
The Serial Interface Engine handles the USB communication protocol. It performs the USB clock/data separation, the NRZI data encoding/decoding, bit stuffing, CRC generation and checking, USB packet ID decoding and generation, and data serialization and de-serialization. The on chip phase locked loop generates the high frequency clock for the clock/data separation circuit.
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Power Management
A hub is a high-powered device and is allowed to draw up to 500 mA of current from the host or upstream hub. The AT43312A chip itself and its external hub circuitry consume much less than 100 mA. The AT43312A's power management logic works with external devices to detect overcurrent and control power to the ports. Overcurrent sensing is on a per-port basis and is achieved through the OVCx pins. Whenever the voltage at OVCx is asserted, the AT43312A treats it as an overcurrent condition. This could be caused by an overload, or even a short circuit and could cause the AT43312A to set the port's PORT_OVER_CURRENT status bit and its C_PORT_OVER_CURRENT status change bit. At the same time, power to the offending port is shut off and its STATx generates a square wave with a frequency of about 1 second. An external device is needed to monitor the overcurrent condition and perform the actual switching of the ports' power under control of the AT43312A. Any type of suitable switch or device is acceptable. However, it should have a low-voltage drop across it even when the port absorbs full-power. In its simplest form this switch can be a P-channel MOSFET. One advantage of using a MOSFET switch is its very low-voltage drop and low-cost. Each one of the AT43312A's port has its own power control pin which is asserted only when a SetPortFeature[PORT-POWER] request is received from the host. PWRx is deasserted under the following conditions: 1. Power-up 2. Reset and initialization 3. Overcurrent condition 4. Requested by the host through a ClearPortFeature [PORT_POWER] for ALL the ports
Self-powered Mode
In the self-powered mode, power to the downstream ports must be supplied by an external power supply. This power supply must be capable of supplying 500 mA per port for a total of 2A. The USB specifications require that the voltage drop at the power switch and board traces be no more than 100 mV. A good conservative maximum drop at the power switch itself should be no more than 75 mV. Careful design and selection of the power switch and PC board layout is required to meet the specifications. When using a MOSFET switch, its resistance must be 140 m or less under worst case conditions. A suitable MOSFET switch for an AT43312A based hub is an integrated high side dual MOSFET switch such as the Micrel MIC2526.
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Bus Powered Mode
In the bus powered mode, all the power for the hub itself as well as the downstream ports is supplied by the root hub or upstream hub through the USB. Only 100 mA is available for each of the hub's downstream devices and therefore only low power devices are supported. The power switch and overcurrent protection works exactly like the self-powered mode, except that the allowable switch resistance is higher: 700 m or less under the worst case condition. The diagrams of Figure 2 and Figure 3 show examples of the power supply and management connections for a typical AT43312A port in the self-powered mode and bus powered mode. Figure 2. Self-powered Hub Power Supply
BUS_POWER GND
U1 GND LPSTAT PWR OVC VCC AT43312A
R1 47K PS5 POWER SUPPLY 5V OUTPUT GND U2
FLG PORT_POWER To Downstream Device
CTL IN
OUT SWITCH
GND
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Figure 3. Bus Powered Hub Power Supply
BUS_POWER GND U1 GND LPSTAT PWR U2 FLG PORT POWER To Downstream Device CTL IN OVC OUT SWITCH GND VCC AT43312A
Port Status Pin
The STATx pins are signals that is not required by the USB specification. Its function is to allow the hub to provide feedback to the user whenever a device is properly connected to the port. An LED and series resistor connected to STATx can be used to provide a visual feedback. If an overcurrent condition is detected at a port, the STATx of the offending port will alternately turn on and off causing an LED to blink. The LED will continue to blink until power to the offending port is turned off by the host or until the hub is re-enumerated. The default state of STATx is inactive. After a port is enabled AT43312A will assert the port's STATx. Any condition that causes the port to be disabled inactivates STATx.
Note: The I/O Pins of the AT43312A should not be directly connected to voltages less than VSS or more than the voltage at the CEXT pins. If it is necessary to violate this rule, insert a series resistor between the I/O pin and the source of the external signal source that limits the current into the I/O pin to less than 2 mA. Under no circumstances should the external voltage exceed 5.5V. To do so will put the chip under excessive stress.
Hub Controller
The Hub Controller of the AT43312A provides the mechanism for the Host to enumerate the Hub and the AT43312A to provide the Host with its configuration information. It also provides a mechanism for the Host to monitor and control the downstream ports. Power is applied, on a per port basis, by the Hub Controller upon receiving a command, SetPortFeature[PORT_POWER], from the Host. The AT43312A must be configured first by the Host before the Hub Controller can apply power to external devices. The Hub Controller contains two endpoints, Endpoint0 and Endpoint1 and maintains a status register, Controller Status Register, which reflects the AT43312A's current settings. At power up, all bits in this register will be set to 0's.
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Table 3. Control Status Register
Bit 0 Function Hub configuration status Value 0 1 0 1 Description Set to 0 or 1 by a Set_Configuration Request Hub is not currently configured Hub is currently configured Set to 0 or 1 by ClearFeature or SetFeature request Default value is 0 Hub is currently not enabled to request remote wakeup Hub is currently enabled to request remote wakeup Endpoint0 is not stalled Endpoint0 is stalled Endpoint1 is not stalled Endpoint1 is stalled
1
Hub remote wakeup status
2 3
Endpoint0 STALL status Endpoint1 STALL status
0 1 0 1
Endpoint 0
Endpoint 0 is the AT43312A's default endpoint used for enumeration of the Hub and exchange of configuration information and requests between the Host and the AT43312A. Endpoint 0 supports control transfers. The Hub Controller supports the following descriptors: Device Descriptor, Configuration Descriptor, Interface Descriptor, Endpoint Descriptor, and Hub Descriptor. These Descriptors are described in detail elsewhere in this document. Standard USB Device Requests and class-specific Hub Requests are also supported through Endpoint 0. There is no endpoint descriptor for Endpoint0.
Endpoint 1
Endpoint1, an interrupt endpoint, is used by the Hub Controller to send status change information to the Host. The Hub Controller samples the changes at the end of every frame at time marker EOF2 in preparation for a potential data transfer in the subsequent frame. The sampled information is stored in a byte wide register, the Status Change Register, using a bitmap scheme. Each bit in the Status Change Register corresponds to one port as shown on the following page. Table 4. Status Change Register
Bit 0 1 2 3 4 5-7 Function Hub status change Port1 status change Port2 status change Port3 status change Port4 status change Reserved Value 0 1 0 1 0 1 0 1 0 1 000 Meaning No change in status Change in status detected No change in status Change in status detected No change in status Change in status detected No change in status Change in status detected No change in status Change in status detected Default values
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An IN Token packet from the Host to Endpoint 1 indicates a request for port change status. If the Hub has not detected any change on its ports, or any changes in itself, then all bits in this register will be 0 and the Hub Controller will return a NAK to requests on Endpoint1. If any of bits 0 - 4 is 1, the Hub Controller will transfer the whole byte. The Hub Controller will continue to report a status change when polled until that particular change has been removed by a ClearPortFeature request from the Host. No status change will be reported by Endpoint 1 until the AT43312A has been enumerated and configured by the Host via Endpoint 0.
Oscillator and PhaseLocked-Loop
All the clock signals required to run the AT43311 are derived from an on-chip oscillator. To reduce EMI and power dissipation in the system, the oscillator is designed to operate with a 6 MHz crystal. An on-chip PLL generates the high frequency for the clock/data separator of the Serial Interface Engine. In the suspended state, the oscillator circuitry is turned off. To assure quick startup, a crystal with a high Q, or low ESR, should be used. To meet the USB hub frequency accuracy and stability requirements for hubs, the crystal should have an accuracy and stability of better than 100 PPM. Even though the oscillator circuit would work with a ceramic resonator, its use is not recommended because a resonator would not have the frequency accuracy and stability. A 6 MHz parallel resonance quartz crystal with a load capacitance of approximately 10 pF is recommended. The oscillator is a special low-power design and in most cases no external capacitors and resistors are necessary. If the crystal requires a higher value capacitance, external capacitors can be added to the two terminals of the crystal and ground to meet the required value. If the crystal used cannot tolerate the drive levels of the oscillator, a series resistor between OSC2 and the crystal pin is recommended. The clock can also be externally sourced. In this case, connect the clock source to the OSC1 pin, while leaving OSC2 pin floating. The switching level at the OSC1 pin can be as low as 0.47V (see Table 8) and a CMOS device is required to drive this pin to maintain good noise margins at the low switching level. Figure 4. Oscillator and PLL Connections
U1 OSC1 OSC2 LFT C2 2nF
Y1 6.000 MHz R1 100 C1 10nF
AT43312A
For proper operation of the PLL, an external RC filter consisting of a series RC network of 100 and 10 nF in parallel with a 2 nF capacitor must be connected from the LFT pin to VSS. To provide the best operating condition for the AT43312A, careful consideration of the power supply connections are recommended. Use short, low-impedance connections to all power supply lines: VCC5, and VSS. Use sufficient decoupling capacitors to reduce noise: 0.1 F decoupling capacitors of high quality, soldered as close as possible to the package pins are recommended. 11
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Power Supply
The AT43312A is powered from the USB bus, but has an internal voltage regulator to supply the 3.3V operating power to its circuitry. For proper operation, an external high quality, low ESR, 0.27 F or larger, capacitor should be connected to the output of the regulator, CEXT pin and ground. The CEXT pin can also be used to supply the voltage to the 1.5K pull-up resistor at Port 0's DP pin. To provide the best operating condition for the AT43312A, careful consideration of the power supply connections are recommended. Use short, low impedance connections to both power supply lines: VCC and VSS. Use sufficient decoupling capacitance to reduce noise: 0.1 F of high quality ceramic capacitor soldered as close as possible to the VCC and VSS package pins. Package pins are recommended. The AT43312A can also operate directly off a 3.3V power supply. In this case, leave the VCC pin floating and connect the 3.3V power to the CEXT pin.
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Electrical Specification
Absolute Maximum Ratings*
Symbol VCC5 VI VO TO TS *NOTICE: Parameter 5V Power Supply DC Input Voltage DC Output Voltage Operating Temperature Storage Temperature -0.3V -0.3 -40 -65 Condition Min Max 5.5 VCEXT + 0.3 4.6 max VCEXT + 0.3 4.6 max +125 +150 Unit V V V C C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
Table 5. Power Supply
Symbol VCC ICC ICCS Parameter 5V Power Supply 5V Supply Current
The values shown in this table are valid for TA = 0C to 85C, VCC = 4.4 to 5.25V, unless otherwise noted.
Condition
Min 4.4
Max 5.25 24 150
Unit V mA A
Suspended Device Current
Table 6. USB Signals: DPx, DMx
Symbol VIH VIHZ VIL VDI VCM VOL1 VOH1 VCRS CIN Parameter Input Level High (driven) Input Level High (floating) Input Level Low Differential Input Sensitivity Differential Command Mode Range Static Output Low Static Output High Output Signal Crossover Input Capacitance RL of 1.5 k to 3.6V RL of 1.5 k to GND 2.8 1.3 DPx and DMx 0.2 0.8 2.5 0.3 3.6 2.0 20 Condition Min 2.0 2.7 0.8 Max Unit V V V V V V V V pF
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Table 7. PWR, STAT, OVC
Symbol VOL2 VOH2 Cout VIL3 VIH3 Cout Parameter Output Low Level, PWR, STAT, OVC Output High Level, PWR Output Capacitance Input Low Level Input High Level Output Capacitance 1 MHz 0.7 VCEXT 10 Condition IOL = 4 mA IOH = 4 mA 1 MHz 0.5 VCEXT 10 0.3 VCEXT Min Max 0.5 Unit V V pF V V pF
Table 8. Oscillator Signals: OSC1, OSC2
Symbol VLH VHL CX1 CX2 C12 tsu DL Note: Parameter OSC1 Switching Level OSC1 Switching Level Input Capacitance, OSC1 Output Capacitance, OSC2 Osc1/2 Capacitance Start-up Time Drive Level 6 MHz, fundamental VCC = 3.3V, 6 MHz crystal, 100 equiv. series resistor Condition Min 0.47 0.67 Max 1.20 1.44 17 17 1 2 150 Unit V V pF pF pF ms W
OSC2 must not be used to drive other circuitry.
Table 9. DPx, DMx Driver Characteristics, Full-speed Operation
Symbol tR tF tRFM zDRV Note: Parameter Rise Time Fall Time TR/TF Matching Driver Output Resistance
(Note:)
Condition CL = 50 pF CL = 50 pF
Min 4 4 90
Max 20 20 110 44
Unit ns ns %
Steady state drive
28
With external 22 series resistor.
Figure 5. Data Signal Rise and Fall Time
RISE TIME VCRS
10% 90% 90%
FALL TIME
10%
DIFFERENTIAL DATA LINES tR tF
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Table 10. DPx, DMx Source Timings, Full-speed Operation
Symbol tDRATEq tFRAME tRFI tRFIADJ Parameter Full Speed Data Rate(1) Frame Interval
(1) (1)
Condition Average Bit Rate
Min 11.97 0.9995
Max 12.03 1.0005 42 126
Unit Mb/s ms ns ns
Consecutive Frame Interval Jitter
No clock adjustment No clock adjustment
Consecutive Frame Interval Jitter(1) Source Diff Driver Jitter
tDJ1 tDJ2 tFDEOP tDEOP
To Next Transition For Paired Transitions Source Jitter for Differential Transition to SEO Transitions Differential to EOP Transition Skew Recvr Data Jitter Tolerance
-2 -1 -2 -2
2 1 5 5
ns ns ns ns
tJR1 tJR2 tFEOPT tFEOPR tFST Note:
To Next Transition To Paired Transitions Source SEO Interval of EOP Receiver SEO Interval of EOP Width of SEO Interval During Differential Transition 1. With 6.000 MHz, 100 ppm crystal.
-18.5 -9 160 82
18.5 9 175
ns ns ns ns
14
ns
Figure 6. Full-speed Load
TxD+
RS CL RS CL
TxD-
CL = 50pF
Table 11. DPx, DMx Driver Characteristics, Low-speed Operation
Symbol tR tF tRFM Parameter Rise Time Fall Time TR/TF Matching Condition CL = 200 - 600 pF CL = 200 - 600 pF Min 75 75 80 Max 300 300 125 Unit ns ns %
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Figure 7. Low-speed Downstream Port Load
TxD+
RS CL RS CL 3.6V 1.5K
TxD-
CL = 200pF to 600pF
Table 12. DPx, DMx Hub Timings, Full-speed Operation
Symbol tHDD2 Parameter Hub Differential Data Delay without Cable Hub Diff Driver Jitter tHDJ1 tHDJ2 tFSOP tFEOPD tFHESK To Next Transition To Paired Transition Data Bit Width Distortion after SOP Hub EOP Delay Relative to THDD Hub EOP Output Width Skew -3 -1 -5 0 -15 3 1 5 15 15 ns ns ns ns ns Condition Min Max 44 Unit ns
Table 13. DPx, DMx Hub Timings, Low-speed Operation
Symbol tLHDD Parameter Hub Differential Data Delay Downstr Hub Diff Driver Jitter tLHDJ1 tLHDJ2 tLUKJ1 tLUKJ2 tSOP tLEOPD tLHESK To Next Transition, downst For Paired Transition, downst To Next Transition, upstr For Paired Transition, upstr Data Bit Width Distortion after SOP Hub EOP Delay Relative to THDD Hub EOP Output Width Skew -45 -15 -45 -45 -60 0 -300 45 15 45 45 60 200 300 ns ns ns ns ns ns ns Condition Min Max 300 Unit ns
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Figure 8. Differential Data Jitter
TPERIOD DIFFERENTIAL DATA LINES CROSSOVER POINTS CONSECUTIVE TRANSITIONS N*TPERIOD+TXJR1 PAIRED TRANSITIONS N*TPERIOD+TXJR2
Figure 9. Differential-to-EOP Transition Skew and EOP Width
TPERIOD DIFFERENTIAL DATA LINES DIFF. DATA-toSE0 SKEW N*TPERIOD+TDEOP SOURCE EOP WIDTH: TFEOPT TLEOPT RECEIVER EOP WIDTH: TFEOPR, TLEOPR CROSSOVER POINT EXTENDED
Figure 10. Receiver Jitter Tolerance
TPERIOD DIFFERENTIAL DATA LINES TJR CONSECUTIVE TRANSITIONS N*TPERIOD+TJR1 CONSECUTIVE TRANSITIONS N*TPERIOD+TJR1 TJR1 TJR2
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Figure 11. Hub Differential Delay, Differential Jitter, and SOP Distortion
UPSTREAM END OF CABLE VSS DIFFERENTIAL DATA LINES VSS HUB DELAY DOWNSTREAM THDD1 CROSSOVER POINT DOWNSTREAM PORT VSS UPSTREAM PORT VSS HUB DELAY UPSTREAM THDD2 CROSSOVER POINT CROSSOVER POINT
50% POINT OF INITIAL SWING
A. DOWNSTREAM HUB DELAY WITH CABLE
B. UPSTREAM HUB DELAY WITHOUT CABLE
DOWNSTREAM PORT VSS UPSTREAM PORT OR END OF CABLE VSS
CROSSOVER POINT
HUB DELAY UPSTREAM THDD1, THDD2
CROSSOVER POINT
C. UPSTREAM HUB DELAY WITH OR WITHOUT CABLE
Figure 12. Hub EOP Delay and EOP Skew
50% POINT OF INITIAL SWING UPSTREAM END OF CABLE VSS DOWNSTREAM PORT VSS A. DOWNSTREAM EOP DELAY WITH CABLE TEOPTEOP+ CROSSOVER POINT EXTENDED UPSTREAM PORT VSS DOWNSTREAM PORT VSS B. DOWNSTREAM EOP DELAY WITHOUT CABLE TEOPTEOP+ CROSSOVER POINT EXTENDED CROSSOVER POINT EXTENDED
DOWNSTREAM PORT VSS UPSTREAM PORT OR END OF CABLE VSS
CROSSOVER POINT EXTENDED
TEOP-
TEOP+
CROSSOVER POINT EXTENDED
C. UPSTREAM EOP DELAY WITH OR WITHOUT CABLE
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Table 14. Hub Event Timings
Symbol tDCNN Parameter Time to Detect a Downstream Port Connect Event Awake Hub Suspended Hub Time to Detect a Disconnect Event and Downstream Port Awake Hub Suspended Hub Time from Detecting Downstream Resume to Rebroadcast Duration of Driving Reset to a Downstream Device Time to Detect a Long K From Upstream Time to Detect a Long SEO From Upstream Time of repeating SEO Upstream Only for a SetPortFeature (PORT_RESET) request 10 2.5 2.5 Condition Min 2.5 2.5 2.5 2.5 Max 2000 12000 2.5 10000 100 20 100 10,000 23 Unit s s s s s ms s s FS bit time
tDDIS
tURSM tDRST tURLK tURLSEO tURPSEO
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330
USB-B C1 0.1UF L10 FB PWR1# L9 18 13 FB 10 OSC1 LPSTAT TEST# DM1 DP1 PWR1# STAT1# OVL1# 0.01UF R4 100 U1 26 27 4 23 17 C4 Y1 6.000 MHZ OVL1# R5 47K
330
J1
330
330
Figure 13. AT43312A Self-powered USB Hub
5
6
CEXT
SELF/BUS#
28
19
C6 0.33UF
9 31
C2 4.7UF
C3 0.1UF
VSS VSS
20
VLOCAL VLOCAL VBUS Q1 2N4401 LED LED D4 R10 D2 R6 1K VLOCAL R7 R8 R9 D1 D3 LED R11 22 DM1R DP1R 22 C9 47pF R12 C10 47pF R13 22 DM2R DP2R PWR2# C11 OVL2# 47pF C12 47pF R14 R15 22 22 DM3R DP3R PWR3# C13 OVL3# 47pF C14 47pF R16 R17 22 22 DM4R DP4R PWR4# OVL4# C15 47pF 22 C5 2.2nF R1 24 25 DM0 DP0 22 11 12 OSC2 LFT DM2 DP2 PWR2# STAT2# OVL2# 32 1 6 21 15 29 30 5 22 16
AT43312A
AT43312A-AC
R2 22 R3 1.5K C7 47pF 8 VCC5 + C8 47pF DM3 DP3 PWR3# STAT3# OVL3# DM4 DP4 PWR4# STAT4# OVL4# 2 3 7 20 14 R18 C16 47pF
1 2 3 4
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5 1 2 3 4 FB 6
OUTA OUTB DM2R 6 + DP2R GND
5
PWR1# PWR2# OVL1# OVL2# MIC2526-2 R20 100K C23 220UFD 10V DM3R + DP3R L3
IN CTLA CTLB FLGA FLGB
C22 0.1UF L12 FB
1 2 3 4
R19 100K
FB 5 JP4 USB-A C24 0.1UF 6 1 2 3 4
R22 100K U4 OUTA OUTB GND 6 8 5 C25 220UFD 10V
R21 100K L4 DM4R + DP4R FB
L13 FB
5
6
PWR3# PWR4# OVL3# OVL4# MIC2526-2
IN CTLA CTLB FLGA FLGB
C26 0.1UF 10 5 1 2 3 4 9 6 7 8 L14 FB RP2 15K
1 2 3 4
C27 0.1UF
R23
1M
6
1255G-USB-05/06
VLOCAL + L1 FB DM1R + C17 4.7UF DP1R C20 0.1UF L11 U3 8 5 L2 C21 220UFD 10V FB C18 0.01UF C19 220UFD 10V JP2 USB-A JP3 USB-A 7 1 4 2 3 JP5 USB-A 7 1 4 2 3
J3
CON2
1 2
Figure 14. AT43312A Self-powered USB Hub
VLOCAL
AT43312A
21
330
USB-B C1 0.1UF 5 L10 FB
330
J1
330
330
Figure 15. AT43312A Bus-powered USB Hub
6
18 13
FB 10 OSC1 LPSTAT TEST# DM1 DP1 PWR1# STAT1# OVL1#
0.01UF
R4 100 U1 26 27 4 23 17
CEXT
SELF/BUS#
28
19
C6 0.33UF
9 31
C2 4.7UF
C3 0.1UF
VSS VSS
22
VBUS VBUS D5 D6 VDD LED 1N4148 D2 D1 R7 R8 R9 R10 D3 D4 1N4148 LED LED R13 22 DM1R DP1R PWR1# L9 C4 Y1 6.000 MHZ OVL1# R14 22 1 2 3 4 R17 22 DM2R DP2R PWR2# OVL2# R18 R21 22 22 DM3R DP3R PWR3# OVL3# R22 R24 22 22 DM4R DP4R PWR4# OVL4# 8 + VCC5 R26 22 DM4 DP4 PWR4# STAT4# OVL4# 2 3 7 20 14 DM3 DP3 PWR3# STAT3# OVL3# C5 2.2nF R1 24 25 DM0 DP0 R2 R3 1.5K 22 22 11 12 OSC2 LFT DM2 DP2 PWR2# STAT2# OVL2# 29 30 5 22 16 32 1 6 21 15
AT43312A
AT43312A-AC
1255G-USB-05/06
DM1R + DP1R C14 0.1UF L11 U3 C15 120UFD 10V L2 DM2R 6 + DP2R C16 0.1UF L12 FB FB OUTA OUTB GND 8 5
5 1 2 3 4 5 6
PWR1# PWR2# OVL1# OVL2# MIC2526-2 R12 47K C17 120UFD 10V DM3R + DP3R L3
IN CTLA CTLB FLGA FLGB
1 2 3 4
R11 47K
FB 5 JP4 USB-A C18 0.1UF 6 1 2 3 4
VDD
R15 47K U4 OUTA OUTB GND 6 + 8 5 C19 120UFD 10V DM4R
R16 47K L4 FB
L13 FB
5
6
PWR3# PWR4# OVL3# OVL4# MIC2526-2
IN CTLA CTLB FLGA FLGB
C20 0.1UF 10 5 1 2 3 4 9 6 7 8 L14 FB RP2 15K
1 2 3 4 DP4R
6
1255G-USB-05/06
C13 120UFD 10V L1 FB JP2 USB-A FB JP3 USB-A 7 1 4 2 3 JP5 USB-A 7 1 4 2 3
Figure 16. AT43312A Bus-powered USB Hub
VBUS
AT43312A
23
Ordering Information
Ordering Code AT43312A-AC AT43312A-SC Package 32AA 32R Operating Range Commercial (0C to 70C)
Green Package Options (Pb/Halid-free/RoHS Compliant)
Ordering Code AT43312A-AU AT43312A-SU Package 32AA 32R Operating Range Industrial (-40C to 85C)
Package Type 32AA 32R 32-lead, Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP) 32-lead, 0.440" Wide, Plastic Gull Wing Small Outline (SOIC)
24
AT43312A
1255G-USB-05/06
AT43312A
Package Information
32AA - LQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 1.35 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM - - 1.40 9.00 7.00 9.00 7.00 - - - 0.80 TYP MAX 1.60 0.15 1.45 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation BBA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32AA, 32-lead, 7 x 7 mm Body Size, 1.4 mm Body Thickness, 0.8 mm Lead Pitch, Low Profile Plastic Quad Flat Package (LQFP) DRAWING NO. 32AA REV. B
R
25
1255G-USB-05/06
32R - SOIC
B
E1
E
PIN 1 e
D
A
A1
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.29 0.102 20.83 14.05 11.05 0.356 0.1 0.53 NOM - - - - - - - - 1.27 TYP MAX 2.54 0.254 21.08 14.40 11.30 0.508 0.22 1.04 Note 1 Note 1 NOTE
0 ~ 8
C
A A1
L
D E E1 B
Note: 1. Dimensions D and E do not include mold Flash or protrusion. Mold Flash or protrusion shall not exceed 0.25 mm (0.010").
C L e
06/04/2002 2325 Orchard Parkway San Jose, CA 95131 TITLE 32R, 32-lead, 0.440" Body Width, Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 32R REV. B
R
26
AT43312A
1255G-USB-05/06
AT43312A
Revision History
Revision Level - Revision Date F - May 2006 Description Added Green package options to Ordering Information
27
1255G-USB-05/06
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